ECC RAM: A Guide to ECC Memory for Industrial Computing

ECC RAM is memory that stores extra check bits alongside the data, so the memory controller can detect and correct errors as data is read. The usual scheme corrects any single-bit error in a 64-bit word and detects, but cannot correct, two-bit errors. Ordinary non-ECC memory has no such check: a flipped bit is passed to the processor as if it were good data.

Most of the time that difference is invisible. Over months of continuous running, with tens of gigabytes of memory, it is not. A single flipped bit can corrupt a logged record, a calculation or a file being written, or crash the operating system with no obvious cause. That is why ECC memory is standard in servers and is often a requirement, not an upgrade, in industrial systems that run unattended for years.

This guide explains how ECC works, the different kinds of ECC that now appear on datasheets (including the on-die ECC built into DDR5), ECC UDIMMs, SO-DIMMs and RDIMMs, which processors and chipsets support ECC, how to check that it is working, and where it earns its place in industrial computing. For the memory basics, see our explainers on RAM and DRAM.

Several different mechanisms are now called ECC. They protect different parts of the memory path, and only some of them give the system the protection and error reporting that the term ECC RAM traditionally means.

The safe way to read a datasheet is to look for the module type (ECC UDIMM, ECC SO-DIMM or RDIMM) or for “in-band ECC”, and to ignore DDR5 on-die ECC when judging data integrity. Our guide to DDR4 vs DDR5 covers the other differences between the two memory generations.

ECC memory uses a Hamming code, a way of calculating check bits from the data so that any single changed bit produces a unique pattern, called a syndrome, when the data is checked again. Standard ECC memory adds one more parity bit to that code so that two-bit errors are also detected. The result is single-error correction, double-error detection, or SECDED.

Writing and reading a word

When the memory controller writes 64 bits of data, it calculates 8 check bits and stores all 72 bits. On a DDR4 ECC module that is why there are nine chips per rank instead of eight. When the data is read back, the controller recalculates the check bits and compares them with the stored ones.

On DDR5 the arithmetic is the same idea at a different width. Each module has two independent 32-bit sub-channels, and an ECC module adds 8 bits to each, so a DDR5 ECC module is 2× 40 bits wide, or 80 bits in all, against 72 bits for DDR4.

Parity memory: the forerunner

Before ECC became common, some PCs used parity memory, which adds one bit per byte so that the total number of ones is always even or always odd. Parity can detect a single flipped bit but cannot say which bit it was, so the only safe response is to stop the system. ECC replaced it because it both finds and repairs the error, and the system keeps running.

Scrubbing and Chipkill

A correctable error left in memory can become an uncorrectable one if a second bit in the same word fails later. Server memory controllers therefore scrub memory, reading through it in the background and writing corrected data back. Server platforms also offer Chipkill, called SDDC (single device data correction) by Intel, which spreads each word across many chips so that the failure of one whole DRAM device can be corrected. It normally needs RDIMMs built from x4 chips.

Memory errors are not only cosmic rays. In practice there are two groups: soft errors, which flip a bit without damaging the chip, and hard errors, which come from a fault in a cell, a connection or a module.

Large field studies show why ECC matters at scale. A widely cited study of Google’s server fleet, published in 2009, found that about a third of machines and more than 8% of DIMMs logged at least one correctable error a year, and that many errors were caused by hardware faults rather than random particle strikes. Soft error rates also rise with altitude, because the neutron flux increases; JEDEC’s JESD89 standard defines how chip makers measure them. The rate for any one module is low, but a fleet of hundreds of computers running for years will see errors, and without ECC nobody knows when or where.

ECC memory comes in the same physical formats as ordinary memory, but the type has to match what the board accepts. Unbuffered and registered modules are not interchangeable. Our explainers on the DIMM and the SO-DIMM cover the formats themselves.

A registered module puts a register clock driver between the memory controller and the DRAM chips, which reduces the electrical load and lets a channel carry more and larger modules, at the cost of about one clock cycle of extra latency. That is why RDIMMs are standard on servers: the Vecow ICS-2000 edge AI server on AMD EPYC 8004 takes six DDR5 4800 RDIMMs for up to 768 GB, and the Winmate SV500S-ML defense rack server takes eight DDR4-3200 RDIMMs on a Xeon Scalable processor.

For vibration, soldered memory removes the socket altogether. The Diamond Systems SATURN PCIe/104 boards offer 8 GB of ECC RAM soldered down, so the module cannot work loose in a vehicle or an airborne system.

ECC is a feature of the memory controller inside the processor, and the chipset and BIOS have to enable it. Many processor families support it only on certain models or with certain chipsets. The table gives typical support; the datasheet of the specific board or computer is the final word.

The chipset matters as much as the processor on Intel desktop-socket designs. The ASRock Industrial IMB-X1714 is an ATX board on the W680 chipset with four ECC or non-ECC DDR5 slots, while its sister board, the IMB-1714, uses the Q670 chipset with non-ECC memory. Same socket, same processors, different memory protection. On AMD, the SolidRun Bedrock V3000 Basic on Ryzen Embedded V3000 takes ECC or non-ECC DDR5-4800 SO-DIMMs, up to 96 GB. For server-class processors, see our guide to AMD EPYC for edge servers.

Arm SoCs and NVIDIA Jetson modules use soldered LPDDR memory, so ECC there is a feature of the SoC and the module design rather than of a removable module. Industrial-grade Jetson modules, such as the Jetson AGX Xavier Industrial module, add ECC on their LPDDR4x memory, enabled in software, alongside a −40 to 85 °C rating, while the standard commercial modules do not. Some NXP i.MX processors, such as the i.MX 8M Plus, support inline ECC on their memory interface, but whether it is enabled depends on the board and its software image.

If an Arm or Jetson design needs ECC, ask for it at the module or SoC selection stage. It cannot be added afterwards, because there is no slot to change.

Several embedded Intel processors, including the Atom x6000E and x7000E series, support in-band ECC. Instead of adding a ninth chip, the memory controller reserves part of ordinary memory for the check bits and reads them along with the data. It gives SECDED protection on modules and soldered memory that have no ECC chips, which makes it useful on compact and low-power designs.

The trade is a little capacity and bandwidth: the check bits take a small share of memory, and each protected read needs an extra access, so some performance is lost on memory-intensive workloads. It is usually enabled in the BIOS and may be off by default. Datasheets list it explicitly: the Nexcom NISE 109 series takes a DDR4 SO-DIMM of up to 16 GB with in-band ECC on its Atom x6211E and Celeron J6412 builds.

Fitting ECC modules does not guarantee ECC is active. If the processor, chipset or BIOS does not support it, most systems run the modules as ordinary memory without warning. Check after the operating system is installed.

Watch the error counts over time. A few corrected errors over months are normal. A steady rise on one module usually means a failing module, and ECC is what keeps the system running until it can be replaced. On servers, the baseboard management controller logs memory errors too, so they can be monitored remotely.

You need ECC where an undetected error would cost more than the memory. The longer a system runs, the more memory it has and the less often anyone looks at it, the stronger the case.

ECC is one part of a reliability case, alongside a watchdog timer, power loss protection on the SSD and memory rated for the operating temperature. Our guide to MTBF explains how component reliability adds up across a system, and what medical grade means covers the medical side.

ECC is not free, but the costs are small and well understood.

The diagnostic benefit is easy to overlook. On a non-ECC fleet, a failing module shows up as occasional crashes that look like software faults, and it can take site visits to find. On an ECC system, the log names the module before it causes a failure. That alone often justifies ECC on computers that are expensive to reach, such as those on railway rolling stock or in remote cabinets.

These systems cover the main ECC options, from registered memory on an edge server to ECC soldered onto a stackable board. We specify the modules with the rest of the build, check that the processor, chipset and BIOS enable ECC, then configure, image and test the computer before it ships, so ECC is confirmed working rather than assumed.

For the wider range, browse our AMD industrial computers, which include many ECC-capable Ryzen Embedded and EPYC designs, and our rack mount servers. For how processor families line up, see our guide to CPU generations and embedded processors.