What Is PCIe?

PCIe, short for PCI Express (Peripheral Component Interconnect Express), is the standard interface that links a computer’s processor and chipset to expansion devices: graphics cards, NVMe SSDs, network cards, capture cards and accelerators. It is maintained by PCI-SIG, the industry group that published the first version in 2003 to replace the older PCI and AGP buses.

PCIe is a point-to-point serial link. Each device gets its own connection rather than sharing a bus, and that connection is made of one or more lanes. A lane is two pairs of wires, one sending and one receiving, so data flows in both directions at once. More lanes means more bandwidth: an x16 link has sixteen lanes and roughly sixteen times the throughput of an x1 link.

The same protocol runs everywhere PCIe appears. A full-size slot, an M.2 socket for an NVMe SSD, a Mini PCIe card and a Thunderbolt tunnel all carry PCIe lanes, just in a different connector.

The number after the x is the slot’s lane count, and the slot’s physical length grows with it. A smaller card always fits a larger slot, so an x1 or x4 card works in an x16 slot. Some boards also use open-ended slots that let a longer card overhang the end.

Figures are usable throughput after encoding, rounded. A standard x16 graphics slot also supplies up to 75 W; cards that need more use auxiliary power connectors.

A slot’s length does not always match its wiring. Many motherboards fit a physical x16 slot that is wired with only eight or four lanes, written as “x16 (x8 electrical)” or “x16 slot with x4 lanes”. The card fits and runs, but at the narrower link width.

This is usually down to the processor’s lane budget. Desktop and embedded processors typically provide 16 to 28 lanes from the CPU plus more from the chipset, and those have to be shared between graphics, M.2 sockets, network chips and slots. The Premio VCO-6000-RPL is a typical example: it has two PCIe x16 slots, each wired with eight Gen4 lanes, so two GPUs or frame grabbers share the processor’s sixteen lanes. Slots wired to the chipset rather than the processor also share the chipset’s own link to the CPU, so several busy cards on chipset slots can compete for bandwidth.

PCIe bifurcation goes one step further, splitting one x16 link into two x8 or four x4 links, set in the BIOS. It lets one slot carry a card with four NVMe SSDs, or feed two slots through a riser. The Premio KCO-6000-ARL uses riser options to choose between one full x16 Gen5 slot or two x16 slots with eight Gen5 lanes each.

Each generation of the specification roughly doubles the data rate per lane while keeping the same slot, so cards and slots from different generations work together at the speed of the slower side. PCIe 3.0 runs at 8 GT/s, about 1 GB/s per lane; PCIe 4.0 at 16 GT/s; PCIe 5.0 at 32 GT/s; and PCIe 6.0 at 64 GT/s, about 8 GB/s per lane.

Our explainers cover the newer generations in depth: what PCIe 5.0 brings for GPUs and SSDs, and how PCIe 6.0 doubles it again with PAM4 signalling.

In an industrial or edge computer, PCIe slots are how a standard chassis is fitted for a specific job.

We fit and test the GPUs, network cards and capture cards each system needs as part of our standard build, matching each card to a slot with enough lanes and power.