FPGA vs ASIC: What Is the Difference?

An FPGA (field-programmable gate array) is a chip made of configurable logic that can be wired into almost any digital circuit after it leaves the factory, and rewired later. An ASIC (application-specific integrated circuit) is a chip whose circuit is fixed when it is manufactured, because it was designed for one job. Both implement hardware logic rather than running software instructions like a CPU, which is why they are compared so often.

The trade-off is flexibility against efficiency. The same FPGA can be a video processor today and a motor controller tomorrow, and it can be fixed with a firmware update. An ASIC does one thing, but it does it faster, in less silicon and with less power, and at high volume each chip costs far less. The catch is the upfront cost and time of designing and manufacturing it, which only large volumes or extreme performance needs can justify.

Inside an FPGA is a grid of small programmable blocks, each built around lookup tables that can mimic any simple logic function, plus flip-flops, connected by a programmable routing network. Larger devices add hard blocks for jobs that would be wasteful in general logic: DSP slices for multiplication, block memory, high-speed serial transceivers, PCIe and Ethernet controllers and, in SoC FPGAs, complete Arm processor cores.

Engineers describe the circuit in a hardware description language such as VHDL or Verilog, or in C++ through high-level synthesis. Vendor tools turn that into a configuration file, the bitstream, which is loaded into the chip at power-up from flash memory. The main FPGA makers are AMD (which acquired Xilinx), Altera, Lattice and Microchip.

An ASIC starts from the same kind of hardware description, but the result is a set of photomasks used to manufacture the chip at a foundry. Most are standard-cell designs built from a library of pre-characterised logic gates. Full-custom design, where transistors are laid out by hand, is kept for the most demanding parts, and structured ASICs sit between an FPGA and a full ASIC by customising only the upper metal layers of a pre-made base.

GPUs often join the comparison, especially for AI. A GPU is a mass-produced programmable processor, so it shares the FPGA’s low entry cost but runs software rather than custom logic.

In practice the three often sit in the same system: an FPGA handles sensor interfaces and timing, an ASIC accelerator runs a fixed AI model at low power, and a GPU handles the workloads that change most often. Our article on what a system on chip is shows how many of these blocks now share one die.

Many ASICs begin life on FPGAs. A design is proven in reconfigurable logic, tested with real data and refined, then moved to an ASIC once the function is stable and the expected volume justifies the NRE. Moving to an ASIC is not a simple conversion: FPGA-specific blocks must be replaced, timing re-verified and test logic added, so allow for real engineering effort.

The opposite route is common in industrial products. Volumes are often in the hundreds or low thousands, interfaces vary from customer to customer and equipment stays in service for 10 years or more, so an FPGA that can be updated in the field is usually the better economic choice. Structured ASICs, or simply staying on the FPGA, cover the middle ground.

Both kinds of chip are common in industrial hardware, usually out of sight. FPGAs do the timing-critical I/O work: many PC/104 I/O modules use an FPGA for digital lines, counters and CAN controllers, and frame grabbers often use one to receive camera data, synchronise triggers and convert video formats before it reaches the host.

ASICs appear most visibly as AI accelerators. Hailo AI accelerators are dedicated ASICs that run vision models at a few watts on an M.2 card, and sealed computers such as the WCO-3000-EHL series take a Hailo-8 module rated at 26 TOPS alongside a low-power Intel processor. Choosing between them is a question of whether the model will change, how much power is available and how many systems you will build.

We build our edge AI and industrial computers with the accelerators, I/O modules and frame grabbers fitted and validated as standard, so the silicon choice is settled before the system ships.