PCIe Generations and Bandwidth: Gen 3 to Gen 7 Explained

PCIe bandwidth roughly doubles with every generation of PCI Express, the serial link that connects graphics cards, NVMe SSDs, network adapters, capture cards and accelerators to a processor. PCIe 3.0 carries about 1 GB/s per lane in each direction; PCIe 7.0, released in 2025, carries about 15 GB/s. The slots look the same from one generation to the next, so the generation, the number of lanes and the way a board shares them decide what a system can really do.

PCI-SIG, the industry group that owns the standard, has kept that doubling going since 2003, but the way it gets there has changed. Up to PCIe 5.0 each generation raised the signalling rate and kept the same packet format. From PCIe 6.0 the link sends two bits per symbol and adds error correction, which matters for anyone designing boards, risers or long cable runs.

This guide is the reference view: a bandwidth table for every generation from Gen 1 to the Gen 8 work in progress, what changed at each step, how lanes, slots and connectors work, where signal integrity and heat start to limit a design, and how to choose and check a generation for an industrial or edge build. For single-generation detail, see our explainers on PCIe 5.0, PCIe 6.0 and PCIe 4.0 vs PCIe 5.0.

The table is the quick reference. Bandwidth is per direction: PCIe links are full duplex, so the same figure flows each way at once, and the combined two-way figure that vendors and PCI-SIG often quote is twice the number shown.

The figures come from the transfer rate and the encoding overhead. PCIe 1.0 and 2.0 spend 2 bits in every 10 on 8b/10b encoding, so 2.5 GT/s gives 250 MB/s per lane. PCIe 3.0 to 5.0 use 128b/130b, which costs about 1.5%. PCIe 6.0 and 7.0 drop line encoding and send data in fixed 256-byte FLITs, about 6% of which is spent on error checking and link control. The PCIe 8.0 figures assume the same FLIT overhead as PCIe 7.0 and will change if the final specification does.

These are theoretical link maximums. Protocol overhead, payload size and the device itself take more, so measured throughput is often 10–20% lower. A PCIe 4.0 x4 NVMe SSD, for example, tops out at around 7 GB/s on sequential reads against the link’s 7.9 GB/s, and a PCIe 5.0 x16 slot gives a GPU about 63 GB/s each way before overheads.

Each generation is backed by a PCI-SIG base specification and a separate electromechanical specification for cards and slots. The headline is always a doubled rate, but the engineering behind it differs.

PCIe 1.0 and 2.0: the serial replacement for PCI

PCI Express replaced the shared parallel PCI and AGP buses with point-to-point serial lanes. Each lane is two differential pairs, one per direction, with the clock embedded in the data using 8b/10b encoding. PCIe 2.0 doubled the rate to 5 GT/s on the same encoding. Both still appear on low-speed controllers inside embedded computers, such as USB and serial bridges on a single lane.

PCIe 3.0: 128b/130b encoding and equalisation

Raising the rate to 10 GT/s with 8b/10b would have been hard on the boards of the time, so PCIe 3.0 moved to 8 GT/s and replaced 8b/10b with 128b/130b encoding plus scrambling. Overhead fell from 20% to about 1.5%, which nearly doubled usable bandwidth. PCIe 3.0 also added transmitter and receiver equalisation, negotiated during link training, to recover signals over longer traces. Many low-power processors still use PCIe 3.0 lanes today.

PCIe 4.0: 16 GT/s and a tighter channel

PCIe 4.0 kept 128b/130b and doubled the rate to 16 GT/s. The tighter loss budget pushed motherboard makers towards lower-loss board materials, and retimers and lane margining became part of the standard tool set for checking a link. The first processors with PCIe 4.0 lanes arrived in 2019, and it is now one of the most common generations in industrial computers.

PCIe 5.0: 32 GT/s and the base for CXL

PCIe 5.0 doubled the rate again to 32 GT/s, still with NRZ signalling and 128b/130b. The specification allows roughly 36 dB of channel loss at that rate, so long traces, risers and backplanes often need a retimer. It also added support for alternate protocols on the same physical layer, which Compute Express Link (CXL) uses. Processors with PCIe 5.0 lanes appeared from late 2021, and PCIe 5.0 SSDs from 2023.

PCIe 6.0: PAM4, FLIT mode and forward error correction

PCIe 6.0 reaches 64 GT/s without raising the signalling frequency. PAM4 signalling uses four voltage levels to send two bits per symbol, so the channel runs at about the same frequency as PCIe 5.0. Four closely spaced levels are more error-prone, so data moves in fixed 256-byte FLITs with a lightweight forward error correction (FEC) and a CRC that triggers a resend if FEC cannot fix an error. PCIe 6.0 also adds the L0p state, which lets a wide link drop lanes when traffic is light without retraining.

PCIe 7.0: 128 GT/s for AI and data-centre links

PCI-SIG released PCIe 7.0 in June 2025. It keeps PAM4 and FLIT mode and doubles the rate to 128 GT/s, giving about 242 GB/s each way on an x16 link. The early targets are AI accelerators, 800G networking and large storage systems, and PCI-SIG is also working on optical connections for PCIe at these rates. Products are expected in data-centre equipment first.

PCIe 8.0: the next work item

In August 2025 PCI-SIG announced that PCIe 8.0 is in development, with a target of 256 GT/s per lane and about 1 TB/s in both directions combined on an x16 link. The group is reviewing new connector technology and has said it aims to keep backward compatibility, with the specification targeted for release by 2028. Until then, treat any PCIe 8.0 figure as a target rather than a specification.

PCIe is backward and forward compatible. When a device and a slot first connect, the two ends train the link at the lowest common rate and then step up to the highest generation and the widest link both support. The result is predictable once you know the rules.

The last row catches people out. A link that trains at a lower speed or width than expected is usually a signal-integrity problem, such as a long riser, a poorly seated card or a cable that is not rated for the generation. On Linux, the LnkCap and LnkSta lines from lspci -vv show the capability and the speed and width the link actually trained to.

Compute Express Link (CXL) is a separate standard that runs over the PCIe physical layer. A CXL device plugs into the same slot or connector and falls back to plain PCIe if the host does not support CXL. It adds two protocols to normal PCIe-style input and output: one that lets an accelerator cache host memory coherently, and one that lets the processor use memory attached to a device as if it were local.

Today CXL matters mainly in servers, where memory expansion modules add capacity beyond the DIMM slots. For most edge systems it is a feature to note on a server processor’s datasheet rather than a deciding factor, but it explains why each new PCIe generation reaches servers first.

A lane is one transmit pair and one receive pair. A link groups 1, 2, 4, 8 or 16 lanes between two devices, written x1 to x16, and bandwidth scales with the lane count. The physical slot is a separate thing: its size sets which cards fit, while the electrical width sets how many lanes are connected.

Datasheets show the difference as “x16 slot (x8 signal)” or “PCIe x16 Gen4 (x4 lanes)”. A full-length slot with fewer lanes lets a full-size card fit in a board that cannot give it all 16 lanes. An open-ended slot has no back wall, so a longer card can sit in a shorter slot and run at the slot’s width.

Slot power is easy to miss in a small chassis. The slot itself supplies up to 75 W; a GPU drawing more needs auxiliary connectors from a power supply rated for it, which is why industrial GPU computers list both the slot generation and the supported card power.

Bifurcation splits one wide link into several narrower ones. An x16 root port can often run as x8/x8, x8/x4/x4 or x4/x4/x4/x4, so a single slot can feed two GPUs through a riser or four NVMe SSDs through a carrier card. It needs support in three places: the processor’s root port, the BIOS setting and the board or riser wiring. A passive carrier card in a slot that cannot bifurcate will show only the first device.

Industrial systems use bifurcation to fit more cards into a small enclosure. The Premio KCO-6000-ARL offers riser options for one PCIe 5.0 x16 slot or two PCIe 5.0 x8 slots, each alongside an x16 slot with four PCIe 4.0 lanes, while the Premio LLM-1U-RPL edge server comes in one-slot x16 and two-slot x8 builds. On the ASRock Industrial iEPF-10000S the two PCIe 5.0 slots run as one x16 or two x8, and the DFI ARS101 Mini-ITX board can split its single PCIe 5.0 x16 slot into two x8 links. A riser card is the usual way to turn those links into physical slots, and the riser must be rated for the generation the link runs at.

Bifurcation is different from a PCIe switch. A switch shares one upstream link between several downstream devices and can give each one a full-width link at times of low load. It adds cost, power and a little latency, but works on root ports that cannot bifurcate.

The processor sets the lane budget, and every slot, M.2 socket and onboard controller takes a share. The table gives typical figures from the processor makers’ published specifications. Board designs vary, so always confirm the lanes a particular computer brings out on its datasheet.

Lanes from the processor go straight to the root complex. Lanes from the chipset share one uplink, which on Intel’s LGA 1700 and LGA 1851 platforms has roughly the bandwidth of a PCIe 4.0 x8 link, so two fast NVMe drives behind the chipset can compete for it. For more on the processor families, see our guides to Intel Core Ultra, AMD EPYC Embedded and the Jetson module guide.

PCIe is not only a card slot. The same lanes run through module sockets, board-to-board connectors and cables, and the connector often decides which generation a design can support.

For the small-form-factor connectors, our explainers cover M.2 keying, the differences between M.2, mSATA and mPCIe, the Mini PCIe card and MXM GPU modules, and the guide to M.2 expansion slots looks at storage, wireless and accelerator cards. Embedded board standards carry PCIe too: see PC/104 bus variants and COM-HPC vs COM Express.

Cabled PCIe is growing because cables lose less signal than long board traces. The Neousys Nuvo-11588 brings a PCIe 4.0 x8 link out through an external SlimSAS port for NVMe storage, PCIe cameras or an external GPU, and the Advantech SKY-MXM-2000B module connects over PCIe 5.0 x8 where there is no room for a full-size card. Over USB4 or Thunderbolt, PCIe is tunnelled with lower bandwidth than a direct link, which suits occasional expansion more than a permanent GPU.

Every doubling of the rate halves the time each bit has on the wire, and copper loses more signal at higher frequencies. The specification sets a loss budget for the whole channel, from the processor pin through the board, connectors and any riser or cable to the device. The budget is roughly constant in decibels, but each decibel buys less trace length as frequency rises.

Two kinds of chip extend a channel. A redriver amplifies and equalises the analogue signal; it is cheap and adds almost no latency, but it boosts noise too and does not reset the loss budget. A retimer recovers the data and clock and transmits a clean signal, so it splits the channel into two budgets. Retimers take part in link training, add a small amount of latency and draw a few watts. The specification allows up to two between a root port and a device.

In rugged systems, signal integrity is also mechanical. A card that moves in its slot under vibration or a riser that flexes can cause errors that a link reports as retries or that force it to train down. Card retention brackets, screw-locked risers and rated cables keep the link at full speed in vehicles and on machines.

Faster links use more power. The clearest example is storage: PCIe 5.0 NVMe SSDs can draw well over 10 W under sustained writes, against a few watts for many PCIe 3.0 drives, and the controller and NAND throttle if they get too hot. In a desktop a small fan over the drive deals with it. In fanless computers there is no airflow, so the heat has to travel through a thermal pad into a heat spreader or the chassis wall.

We size storage to the workload. If the application records video at a few hundred megabytes per second, a PCIe 4.0 or even 3.0 SSD has the bandwidth with far less heat, and stays clear of thermal throttling at the top of the temperature range. Where a build needs PCIe 5.0 storage, we specify drives rated for the temperature range and a thermal path, such as a heat spreader with conduction cooling to the enclosure, that suits the drive’s power. The same applies to retimers, 100GbE network cards and GPUs, which all add heat that a sealed chassis has to remove.

Interface choice matters too. Our explainer on NVMe and SATA on M.2 covers when a SATA SSD is still the better fit for a low-power, high-temperature computer.

Start from the bandwidth each device needs, then find the narrowest link that carries it with some margin. Network bandwidth converts at eight bits to the byte, so a 10 Gb/s port needs about 1.25 GB/s.

A worked example: a vision system with four 10GbE cameras needs about 5 GB/s into the computer. That fits a PCIe 3.0 x8 or PCIe 4.0 x4 network card with room to spare. Add a GPU on PCIe 4.0 x16 and an NVMe SSD on x4, and the build needs 28 lanes or more, which rules out most low-power processors and points to an Intel Core, AMD Ryzen or server processor. The network interface card and capture card in that build will usually run at full speed on PCIe 4.0; the reason to choose PCIe 5.0 is to give the GPU or storage more headroom, or to fit the same bandwidth into fewer lanes.

For most industrial and edge projects today, PCIe 4.0 is the safe default and PCIe 5.0 is worth choosing for high-end GPUs, fast storage and 100GbE and faster networking. PCIe 6.0 is arriving in data-centre switches, network cards and SSDs, and we expect it to reach rugged edge AI servers once server processors support it.

These systems show how the generation and lane budget translate into real slot layouts. We fit the GPUs, network and capture cards, configure the BIOS for the right bifurcation and link speed, image the operating system and test the computer with the cards fitted before it ships. Further options sit in our Premio range and in PCIe expansion cards for adding ports to an existing system.

Not every build needs PCIe 5.0. Many PCIe video capture cards and frame grabbers are PCIe 2.0 or 3.0 designs, and a compact computer with a PCIe 4.0 slot is often the better fit when space, power and temperature are tighter than the bandwidth budget. For a full rack system, an edge server on server motherboards with more lanes may be the simpler route.