US What a CPU cache is
A CPU cache is a small amount of very fast memory built into the processor that holds copies of the data and instructions the cores are most likely to need next. It is made from static RAM (SRAM), which is far quicker than the dynamic RAM used for main memory but takes much more silicon per bit, so caches are measured in kilobytes and megabytes rather than gigabytes.
The reason caches exist is a speed gap. A modern core can complete an operation in a fraction of a nanosecond, while fetching data from main memory typically takes around 80 to 100 ns. Without a cache, the core would spend most of its time waiting. With one, most requests are answered on the chip in a few cycles.
Cache memory is also called a CPU memory cache. It has nothing to do with a web browser’s cache, which stores downloaded files on the drive.
L1, L2 and L3 cache explained
Processors arrange cache in levels. Each level further from the core is larger and slower. When a core needs data, it checks L1 first, then L2, then L3, and only goes to main memory if none of them has it.
| Level | Where it sits | Typical size | Typical latency | Shared or private |
|---|---|---|---|---|
| L1 cache | Inside each core, split into instruction and data | Around 32 to 64 KB each | Around 4 to 5 cycles, about 1 ns | Private to one core |
| L2 cache | Next to each core or core cluster | Around 512 KB to 3 MB | Around 12 to 18 cycles | Per core, or per cluster of efficient cores |
| L3 cache | On the die, shared by all cores | Around 4 MB to 36 MB, more on server and stacked-cache chips | Around 40 to 70 cycles | Shared |
| Main memory | DRAM modules or soldered chips | Gigabytes | Around 80 to 100 ns | Shared by the whole system |
Sizes vary between families, so read the exact processor’s datasheet. Low-power embedded processors usually carry less L3 than desktop and server parts, and some chips add a further cache or a system-level cache shared with the graphics.
How a cache decides what to keep
Caches work because programs are predictable. Code tends to reuse the same data soon after it first touches it, and to read data that sits next to what it just read. The cache exploits both habits.
-
//
Cache line. Data moves between memory and cache in fixed blocks, usually 64 bytes, so neighboring data arrives with the byte that was asked for.
-
//
Cache hit. The data is already in the cache and returns in a few cycles.
-
//
Cache miss. The data is not there, so the core waits while it is fetched from the next level or from main memory.
-
//
Hit rate. The share of requests answered by the cache. Well-behaved code often hits L1 more than 90% of the time.
-
//
Prefetching and eviction. Hardware prefetchers fetch data before it is requested, and replacement rules decide which old lines to drop when the cache is full.
How cache size affects performance
More cache helps when a workload’s working set, the data it touches repeatedly, is larger than the cache it has. Databases, simulation, compilers, games and the pre- and post-processing stages of AI pipelines all benefit from a larger L3. Simple control loops that fit comfortably in L1 and L2 see little difference. On a multi-core processor, coherency logic also keeps every core’s private cache in step, so a value one core changes is never read stale by another.
Cache is one reason a newer processor can beat an older one at the same clock speed. Our guide to CPU generations and embedded processors covers how cache, cores and graphics change between generations. When the cache misses, memory bandwidth takes over, which is where the move to faster memory described in our DDR4 vs DDR5 comparison pays off.
Server processors such as AMD EPYC carry tens of megabytes of L3, while low-power embedded chips trade cache for lower power and cost.
Cache in real-time and industrial systems
In a real-time controller, the problem with cache is not average speed but variation. If another task evicts the control loop’s data from the shared L3, the next cycle takes longer, and that jitter can break a strict cycle time.
Intel addresses this with Cache Allocation Technology, which reserves part of the L3 for chosen cores or tasks, and with Time Coordinated Computing (TCC) on selected embedded processors, including the Intel Elkhart Lake family. Combined with core isolation and a real-time kernel, cache partitioning keeps latency predictable for motion control, robotics and time-sensitive networking.
Quick answers on CPU cache
CPU cache: common questions
What does L3 cache do?
It is the large shared cache for all cores. L3 catches requests that miss L1 and L2, so cores go to main memory less often, and it lets cores share data without a trip to memory.
Is cache memory the same as RAM?
No. Cache is SRAM inside the processor, measured in kilobytes and megabytes. RAM is DRAM on modules or soldered chips, measured in gigabytes and many times slower.
Can you upgrade a CPU cache?
No. The cache is part of the processor die. The only way to get more is to choose a processor with more.
Is more L3 cache always better?
Only if the workload uses it. Large data sets gain a lot. Small control tasks that already fit in L2 gain little, and a bigger cache adds cost and power.
Why is cache faster than main memory?
It is closer and built differently. SRAM holds each bit in a few transistors with no refresh, and it sits on the same die as the cores, so data travels a few millimeters instead of across the board.
We specify the processor family for each industrial computer we build by its cache, cores and memory as well as its clock, and set cache partitioning and core isolation where the application needs real-time behavior.