PCIe/104 replaces the parallel buses with PCI Express and, with it, the bandwidth needed for 10G Ethernet, cameras, NVMe storage and accelerators. The connector is defined in two heights, 0.600 in (15.24 mm) and 0.866 in (22.00 mm), so that the stack pitch and signal integrity rules of the older buses are preserved. The initial specification was adopted in March 2008; revision 2.1, approved in February 2013, added the rules for PCI Express Gen 2 and Gen 3.
Two connector types share a common core. Both carry four x1 PCI Express links, two USB 2.0 ports, the ATX power control signals (+5 V standby, power supply on and power OK), the +3.3 V, +5 V and +12 V rails and an SMBus. Type 1 adds one x16 PCI Express link that can be configured as two x8 links or two x4 links, which suits graphics and the highest-bandwidth I/O. Type 2 replaces the x16 with two x4 PCI Express links and adds two USB 3.0 ports, two SATA ports, an LPC bus and an RTC battery signal, which suits storage and general-purpose I/O. A module built for one type will not find the links it expects on a host of the other, so the type is a selection decision, not a detail.
Two features make the bus practical in a stack. Automatic link shifting means each module takes the first PCI Express link presented to it and shifts the remainder to the next connector, so an add-in module needs no configuration and can sit at any position. The specification also supports stack-up and stack-down arrangements, so modules can be placed on either side of the host as the enclosure dictates.